1. Field of the Invention
The present invention relates to an electrostatic discharge protection element for protecting a semiconductor device having a high withstanding voltage from breakdown due to a surge or noise represented by electrostatic discharge or the like.
2. Description of the Related Arts
A semiconductor device is equipped with an electrostatic discharge (hereinafter, briefly referred to as ESD) protection element for protecting internal elements from various surges or noises represented by ESD. Examples of the ESD protection element include a diode element, which is parasitically formed, a bipolar element, and a thyristor element. A function required to those elements is to hold constantly an off-state during a steady state, to operate before occurrence of a breakage of an internal element upon application of a surge or noise to a semiconductor device, to discharge a large current generated by the surge or noise, and to return to the off-state again.
As a general ESD protection element, an NMOS off transistor is exemplified. FIG. 6 illustrates a conventional NMOS off transistor. The NMOS off transistor of FIG. 6 is formed on a p-type semiconductor substrate 11, and includes a gate electrode 33 on a gate insulating film 22 formed on the p-type semiconductor substrate 11. An n-type high concentration diffusion layer 15a is formed on a drain electrode 31. An n-type high concentration diffusion layer 15b to serve as a source and a p-type high concentration diffusion layer 16 to take a potential of the p-type semiconductor substrate 11 are formed for a source-substrate substrate electrode 32. The n-type high concentration diffusion layer 15b, the p-type high concentration diffusion layer 16, and the gate electrode 33 are electrically connected to one another, and connected to a potential Vss. The drain electrode 31 is connected to a power supply terminal Vdd or an input/output terminal.
The NMOS off transistor of FIG. 6 has the following structure. When a negative polarity surge or noise is applied to the drain electrode 31, a forward bias is generated in a pn junction of the n-type high concentration diffusion layer 15a and the p-type semiconductor substrate 11, whereby charges are escaped to the Vss. When a positive polarity surge or noise is applied to the drain electrode 31, a generated reverse bias causes surface breakdown, and the source, the substrate, and the drain parasitically form an npn bipolar transistor, which is operated by a current flowing in the p-type semiconductor substrate 11, whereby a large current is escaped to the Vss. In order to reliably turn off the NMOS off transistor after the discharge of the surge or noise, it is important in the operation of the parasitic npn bipolar transistor to set a holding voltage to a value equal to or larger than a maximum operating voltage applied to the semiconductor device. According to a conventional structure, the holding voltage may be set with ease by adjusting an L length of the NMOS transistor. JP 2007-214267 A is described below as an example of such a structure.
In a case where the withstanding voltage of a semiconductor device to be protected is high, a high voltage is naturally required for a surface breakdown voltage and a holding voltage of an NMOS transistor. FIG. 7 illustrates an NMOS off transistor in which a drain electrode has a high withstanding voltage structure. The NMOS off transistor of FIG. 7 is formed on a p-type semiconductor substrate 11, and includes a gate electrode 33 on a gate insulating film 22 formed on the p-type semiconductor substrate 11. The NMOS off transistor of FIG. 7 has a LOCOS offset structure in which LOCOS oxide films 21a and 21b and n-type channel stop diffusion layers 13a and 13b are formed at both ends of the gate electrode 33. An n-type high concentration diffusion layer 15a and an n-type well diffusion layer 12 are formed on the drain electrode 31. The n-type well diffusion layer 12 is formed in order to mitigate electric field concentration, which is generated in a lower region of the n-type high concentration diffusion layer 15a when a high voltage is applied to the drain electrode 31. An n-type high concentration diffusion layer 15b to serve as a source and a p-type high concentration diffusion layer 16 to take a potential of the p-type semiconductor substrate 11 are formed for a source-substrate electrode 32. The n-type high concentration diffusion layer 15b, the p-type high concentration diffusion layer 16, and the gate electrode 33 are electrically connected to one another, and connected to a potential Vss. The drain electrode 31 is connected to a power supply terminal Vdd or an input/output terminal.
It is necessary to increase a junction withstanding voltage with the semiconductor substrate and a surface breakdown voltage with respect to the drain electrode, and hence an impurity concentration of the semiconductor substrate cannot be set to be excessively high. As the required withstanding voltage becomes higher, the concentration of the semiconductor substrate becomes lower. In FIG. 7, the NMOS off transistor is a high withstanding voltage protection element, and hence the concentration of the p-type semiconductor substrate 11 is extremely low. That is, the p-type semiconductor substrate 11 has a high resistance. Accordingly, when a positive polarity surge or noise is applied to the drain electrode 31, a current generated due to surface breakdown easily causes an increase in potential of the p-type semiconductor substrate 11 located below the n-type high concentration diffusion layer 15b and an n-type channel stop diffusion layer 13b, which easily sets an parasitic npn bipolar transistor into operation. As a result, there arises a problem that the holding voltage becomes extremely low.
As in the conventional structure, when the holding voltage is adjusted based on the L length of the NMOS transistor, a size of the NMOS off transistor increases. There may be conceived a method of enhancing the drain withstanding voltage by adjusting the thickness of the gate insulating film 22 and the concentration of the n-type diffusion layer of the drain electrode, to thereby increase the concentration of the p-type semiconductor substrate 11. However, according to the method, the structure of those components is greatly different from that of an internal element, which increases manufacturing steps. Further, the semiconductor device to be protected has a high withstanding voltage, and hence a difference between the maximum operating voltage and the holding voltage is increased when the holding voltage becomes extremely low. Accordingly, even with the use of the above-mentioned method, it is difficult to set the holding voltage equal to or larger than the maximum operating voltage.